Hitachi, Ltd. (NYSE: HIT / TSE: 6501) in cooperation with Elpida Memory, Inc. (TSE: 6665), have proposed a new DRAM(*1) circuit design enabling 0.4-V operation. The proposed array employs a twin cell ...

Fremont, Calif. – Graphics could be processed faster by breaking up the DRAM array into a bunch of smaller independent arrays with separate row and column decoders, Rambus engineers suggest. In a ...

Embedded DRAM technology offers many advantages in System On Chip products. Computing applications demand memory with low latency and zero soft error rate. Graphics ...

This picture was taken by using a DRAM chip as an image sensor (translated). A decapped 64k DRAM chip was combined with optics that could focus an image onto the die. By reading data out of the DRAM, ...

With the new round, total funding in Newton, Mass.-based Kaminario comes to $65 million. Kaminario is a developer of an all solid-state Flash and DRAM SAN storage solution, the Kaminario K2, which was ...

NEO Semiconductor has unveiled its "3D X-DRAM", which it is pitching as the world's first 3D NAND-like DRAM cell array. Based on Neo's estimates, 3D X-DRAM technology can achieve 128 Gb density with ...

For applications where performance is of primary importance, designers have traditionally chosen SRAM technology over DRAM. Although commodity DRAM offers much higher density and a lower cost per bit, ...

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers ...

Imec has come up with a novel DRAM cell architecture that implements two indium-gallium-zinc-oxide thin-film transistors (IGZO-TFTs) and no storage capacitor. DRAM cells in this 2T0C (2 transistor 0 ...