EDN

Matching ESD protection to process geometry

Advanced CMOS process technologies enable IC designers to deliver higher performing devices, but also increase the need for extra board-level ESD protection to ensure the reliability of the end ...
Design-Reuse

Sarnoff's 65nm CMOS TakeCharge ESD Solution licensed to Fujitsu, Japan

GISTEL, Belgium -- November 17, 2006 -- Sarnoff Europe (www.sarnoffeurope.com) today announced that it has licensed its on-chip electrostatic discharge (ESD) protection portfolio, TakeCharge® to ...
EDN

Knee deep in exploding mice

I was asked to help out a co-worker, “Joe”, a less-experienced engineer, with an ESD problem. Highly appropriate, after all, I had five whole years of work under my belt. The product was only a ...
Electronics Weekly

Input structure boosts analogue ESD protection

Toshiba has revealed details of an electrostatic discharge (ESD) protection scheme for 0.13μm analogue power semiconductors. “ESD protection is much more robust, up four times, and the standard ...
Nanowerk

World's first vertically stacked gate-all-around Si nanowire CMOS transistors

(Nanowerk News) At this week’s IEEE IEDM conference, world-leading research and innovation hub for nano-electronics and digital technology, imec, reported for the first time the CMOS integration of ...
Electronics Weekly

Imec makes CMOS GAA nanowire mosfets

Imec has achieved the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs. Key in the integration scheme is a dual-work-function metal gate enabling matched threshold ...
Electronic Design

It’s Hot, Powering, And Burning CMOS Logic Circuits

Fig 1. A typical CMOS input circuit comprises a “P” and “N” transistor. One is fully “on” for logic high, and the other is “on” for a logic low. Fig 2. When a CMOS input pin is at logic high or low ...